1. Field of the Invention
The present invention relates to an on-die termination circuit mounted as a termination circuit in LSI (Large Scale Integration).
2. Description of the Related Art
In recent years, the demand for LSI having higher speeds, greater bandwidth operation, and lower power consumption continues to grow, and the transfer bus inside an LSI must therefore be treated as a high-speed transmission path. The demand for miniaturization of LSI is also growing, and with this demand comes a growing need for mounting on-die termination circuits as termination circuits for terminating the transfer bus to absorb reflection of bus signals transmitted in the transfer bus in the LSI. Recently, devices in which on-die termination circuits are mounted such as DDR2 SDRAM (Double Data Rate 2-Synchronous Dynamic Random Access Memory) are being manufactured.
In an on-die termination circuit, the termination resistance, which is the impedance of the entire on-die termination circuit with respect to a terminal connected to the transfer bus, in some cases diverges from the target value due to variations that occur during manufacturing. Thus, from the standpoints of maintaining characteristics and ensuring yield, the on-die termination circuit must therefore be provided with the capability for adjustment of the termination resistance, and from the standpoint of reducing power consumption, must further be provided with the capability to turn off the on-die termination circuit when the operation is halted.
FIG. 1 shows the configuration of an on-die termination circuit according to the first example of the prior art. This configuration can be readily deduced from the technology disclosed in JP-A-2002-152032.
As shown in FIG. 1, the on-die termination circuit of the first example of the prior art is composed of only transistors p1˜p5, which are PMOS transistors, and is of a configuration in which transistors p1˜p5 are connected together in parallel.
Control signals 1˜5 are applied as input to the gate terminals of transistors p1˜p5, respectively, and control signals 1˜5 control the ON/OFF states of transistors p1˜p5. The terminal pin is the terminal that connects the on-die termination circuit to the transfer bus. Vswing represents the difference in potential across the two ends of the on-die termination circuit, i.e., the voltage of the termination pin and the termination voltage (assumed to be the power supply voltage VDD in FIG. 1).
However, because the on-die termination circuit of the first example of the prior art shown in FIG. 1 is composed solely of transistors p1˜p5 which are PMOS transistors, the circuit suffers from the problem that the impedance varies widely according to the voltage level of Vswing due to the characteristics of MOS transistors.
FIG. 2 shows the typical IDS-VDS characteristic of a MOS transistor.
As shown in FIG. 2, when a MOS transistor is used as a resistance element, the resistance can be considered as linear resistance similar to the resistance in normal wiring in the linear region, and particularly in the linear region in which VDS is low. However, in the linear region in which VDS increases and approaches the saturation region, the change in resistance becomes nonlinear and can no longer be treated as normal linear resistance.
Vswing shown in FIG. 1 varies according to various standards, but is equal to the power supply voltage in SDRAM, DDR-SDRAM, and DDR2-SDRAM, and Vswing therefore can attain a high value. Vswing attains a high value because, according to the standards in SDRAM, a voltage is delivered ranging from GND to the power supply voltage and the termination voltage is made the same voltage as the power supply voltage of the SDRAM. When the on-die termination circuit according to the first example of the prior art is mounted in an SDRAM, VDS exceeds “VGS-Vth” and transistors p1˜p5 therefore operate in the saturation region, whereby the termination resistance can no longer be maintained at a fixed value. Consequently, the reflection of the bus signals transferred through the transfer bus has an adverse effect on signal transmission.
In RDRAM (Rambus DRAM), in which the amplitude is smaller than for SDRAM, Vswing is in the order of 1V. When the on-die termination circuit according to the first example of the prior art is mounted in RDRAM and if the threshold voltage Vth of transistors p1˜p5 is set to the order of 0.7V, transistors p1˜p5 operate in the linear region until the power supply voltage reaches the level of 2.5V. If operation at low voltage is desired for the sake of reducing power consumption, however, transistors p1˜p5 will operate in the saturation region as described above when the power supply voltage reaches the level of 1.8V, and the termination resistance can no longer be maintained at a fixed level.
However, from the standpoint of lowering power consumption, the capability to place the on-die termination circuit in the OFF state is required in an on-die termination circuit as described hereinabove, and a configuration that employs transistors as switch elements is therefore necessary.
Accordingly, a configuration cannot be adopted in which termination resistance that depends only on resistor element r1 is adjusted by transistor p1, as in the configuration of the second example of the prior art shown in FIG. 3. This configuration is similar to the configuration disclosed in JP-A-1999-55104.
The following explanation regards an on-die termination circuit that provides a solution to the above-described drawback, i.e., that can reduce the fluctuation in the termination resistance in accordance with Vswing voltage level, and moreover, that can set the on-die termination circuit to the OFF state.
FIGS. 4A and 5A show the configuration of the on-die termination circuit of the third example of the prior art. In FIGS. 4A and 5A, the composition of the circuits are identical, but the transistors that turn ON during adjustment of termination resistance differ. In addition, FIG. 4B shows an equivalent circuit diagram in which FIG. 4A is represented by resistor elements and capacitance elements, and FIG. 5B shows an equivalent circuit diagram in which FIG. 5A is represented by resistor elements and capacitance elements.
As shown in FIGS. 4A and 5A, the on-die termination circuit of the third example of the prior art is of a configuration in which five sets of unit circuits, in which resistor elements and transistors are connected in a series, are connected together in parallel.
Control signals are applied as input to the gate terminals of transistors p1˜p5, which are PMOS transistors, and transistors p1˜p5 are thus switched ON and OFF by these control signals. However, in order to clarify whether transistors p1˜p5 are ON or OFF, the following figures show GND connected to the gate terminals of transistors p1˜p5 when the transistors are ON and the power supply connected when the transistors are OFF. Further, of the voltage difference Vswing between the two ends, VswingR indicates the voltage difference that depends on resistor elements, and Vswing p indicates the voltage difference that depends on transistors.
In all unit circuits rsum1˜rsum5, the resistance ratios of the resistor elements and transistors are substantially equal. Here, the ratio of the resistance of a resistor element to the resistance of a transistor is 4:1. Accordingly, because the resistance of a transistor is ⅕ of the total, fluctuation in the termination resistance that originates from fluctuation in Vswing can be reduced.
In addition, unit circuits rsum1˜rsum5 are of a binary configuration in which impedance values Rsum1˜Rsum5 of each of unit circuits rsum1˜rsum5 have the following relation:Rsum1=Rsum2/2=Rsum3/4=Rsum4/8=Rsum5/16
If PW is the width w of transistor p1, then the widths w of transistors p2, p3, p4 and p5 are PW/2, PW/4, PW/8, and PW/16, respectively. If R1 is the resistance of resistor element r1, resistances R2, R3, R4, and R5 of resistor elements r2, r3, r4, and r5 are 2×R1, 4×R1, 8×R1, and 16×R1, respectively. If Rp1 is resistance of resistance component rp1 of transistor p1, then resistances Rp2, Rp3, Rp4, and Rp5 of resistance components rp2, rp3, rp4, and rp5 of transistors p2, p3, p4 and p5 are 2×Rp1, 4×Rp1, 8×Rp1, and 16×Rp1, respectively. Further, if Cp1 is the capacitance of capacitance component cp1 of transistor p1, then capacitances Cp2, Cp3, Cp4, and Cp5 of capacitance components cp2, cp3, cp4, and cp5 of transistors p2, p3, p4, and p5 are Cp1/2, Cp1/4, Cp1/8, and Cp1/16, respectively.
FIG. 4A shows the state in which two transistors p1 and p2 are ON and the termination resistance of the entire on-die termination circuit with respect to the terminal pin is adjusted to 50Ω. In this case, R1 is assumed to be 60Ω (Rp1=R1/4=15Ω, and Rsum1=R1+Rp1=75Ω). In contrast, FIG. 5A shows the state in which, because the termination resistance has been fabricated at a low level, the two transistors p1 and p3 are turned ON to adjust the termination resistance to 50Ω. In this case, R1 is assumed to be in the order of 50Ω.
In the case of FIG. 4A, considering the frequency characteristic, impedances Rsum1˜Rsum5 of unit circuits rsum1˜rsum5 can be represented as shown below. Both here and in subsequent equations, s=jω.
            Rsum      ⁢                          ⁢      1        =                  R        ⁢                                  ⁢        1            +              (                              Rp            ⁢                                                  ⁢            1                    //                      1            /                          (                              sCp                ⁢                                                                  ⁢                1                ⁢                on                            )                                      )                        Rsum      ⁢                          ⁢      2        =                            R          ⁢                                          ⁢          2                +                  (                                    Rp              ⁢                                                          ⁢              2                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  2                  ⁢                  on                                )                                              )                    ⁢                          ⁢                          =                        2          ×          R          ⁢                                          ⁢          1                +                  (                                    2              ×              Rp              ⁢                                                          ⁢              1                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  1                  ⁢                                      on                    /                    2                                                  )                                              )                                Rsum      ⁢                          ⁢      3        =                            R          ⁢                                          ⁢          3                +                  1          /                      (                          sCp              ⁢                                                          ⁢              3              ⁢              off                        )                              =                        4          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                4                                      )                                          Rsum      ⁢                          ⁢      4        =                            R          ⁢                                          ⁢          4                +                  1          /                      (                          sCp              ⁢                                                          ⁢              4              ⁢              off                        )                              =                        8          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                8                                      )                                          Rsum      ⁢                          ⁢      5        =                            R          ⁢                                          ⁢          5                +                  1          /                      (                          sCp              ⁢                                                          ⁢              5              ⁢              off                        )                              =                        16          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                16                                      )                              
Similarly, in the case of FIG. 5A, the impedances Rsum1˜Rsum5 of unit circuits rsum1˜rsum5 that take the frequency characteristic into consideration can be represented as follows:
            Rsum      ⁢                          ⁢      1        =                  R        ⁢                                  ⁢        1            +              (                              Rp            ⁢                                                  ⁢            1                    //                                    1              /              sCp                        ⁢                                                  ⁢            1            ⁢            on                          )                        Rsum      ⁢                          ⁢      2        =                            R          ⁢                                          ⁢          2                +                  1          /                      (                          sCp              ⁢                                                          ⁢              2              ⁢              off                        )                              =                        2          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                2                                      )                                          Rsum      ⁢                          ⁢      3        =                            R          ⁢                                          ⁢          3                +                  (                                    Rp              ⁢                                                          ⁢              3                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  3                  ⁢                  on                                )                                              )                    ⁢                          ⁢                          =                        4          ×          R          ⁢                                          ⁢          1                +                  (                                    4              ×              Rp              ⁢                                                          ⁢              1                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  1                  ⁢                                      on                    /                    4                                                  )                                              )                                Rsum      ⁢                          ⁢      4        =                            R          ⁢                                          ⁢          4                +                  1          /                      (                          sCp              ⁢                                                          ⁢              4              ⁢              off                        )                              =                        8          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                8                                      )                                          Rsum      ⁢                          ⁢      5        =                            R          ⁢                                          ⁢          5                +                  1          /                      (                          sCp              ⁢                                                          ⁢              5              ⁢              off                        )                              =                        16          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                16                                      )                              
In addition, the impedance RTerm of the entire on-die termination circuit with respect to the terminal pin can be represented as follows:RTerm=Rsum1//Rsum2//Rsum3//Rsum4//Rsum5
FIG. 6 shows the result of plotting RTerm against frequency for the two cases of FIG. 4A and FIG. 5A.
As shown in FIG. 6, R_lower, which is the minimum value of RTerm, is the point at which impedance stabilizes in the high-frequency region. R_lower shown in FIG. 6 shows the value of R_lower for the case of FIG. 4A. This R_lower can only be approximated by resistances R1˜R5 of resistance elements r1˜r5 in the equation above, and in the cases of both FIG. 4A and FIG. 5A, converges on the resistance of RTerm when only resistor elements r1˜r5 are connected together in parallel.
In other words, impedance RTerm of the high-frequency region for the case of FIG. 4A can be represented as follows:
  RTerm  =                                                        R              ⁢                                                          ⁢              1                        //                          R              ⁢                                                          ⁢              2                                //                      R            ⁢                                                  ⁢            3                          //                  R          ⁢                                          ⁢          4                    //              R        ⁢                                  ⁢        5              ⁢                  ⁢                  =                                        60            //            120                    //          240                //        480            //              960        ⁢                                  ⁢                                  ≈                  30          ⁢                                          ⁢          Ω                    
Impedance RTerm of the high-frequency region for the case of FIG. 5A can be similarly represented as follows:
  RTerm  =                                          R            ⁢                                                  ⁢            1                    //                      R            ⁢                                                  ⁢            2            ⁢                          //                        ⁢            R            ⁢                                                  ⁢            3                          //                  R          ⁢                                          ⁢          4                    //              R        ⁢                                  ⁢        5              ⁢                  ⁢                  =                                        50            //            100                    //          200                //        400            //              900        ⁢                                  ⁢                                  ≈                  25.8          ⁢                                          ⁢          Ω                    
The frequency dependence of the termination resistance is therefore great in the third example of the prior art, and in either of the cases of FIG. 4A and FIG. 5A, impedance RTerm at which stability is attained in the high-frequency region is considerably lower than the target of 50Ω.
In addition, for the case of FIG. 4A and the case of FIG. 5A, the transistors that are switched ON during the adjustment of the termination resistance differ and the parasitic element configuration of these parts therefore also differs, and as a result, the frequency characteristic changes and the impedance RTerm at which stability is attained differs greatly. Considering the resistance of resistor element r2 and the size (width) of transistor p2, unit circuit rsum2 that is ON in FIG. 5A when compared with unit circuit rsum3 that is ON in FIG. 4A can be considered to have an additional resistor element having high resistance and capacitance element having high capacitance. As a result, the impedance RTerm in FIG. 5A is lower in the low-frequency region than in FIG. 4A.
FIG. 7A and FIG. 8A show the configuration of an on-die termination circuit according to a fourth example of the prior art. Although the circuit configurations are identical in FIG. 7A and FIG. 8A, the transistors that are ON during adjustment of the termination resistance differ. In addition, FIG. 7B shows an equivalent circuit diagram in which FIG. 7A is represented by resistance elements and capacitance elements, and FIG. 8B shows an equivalent circuit diagram in which FIG. 8A is represented by resistance elements and capacitance elements.
As shown in FIG. 7A and FIG. 8A, the on-die termination circuit of the fourth example of the prior art is a configuration composed of resistance element r0 and transistors p1˜p5, which are PMOS transistors that are both connected together in parallel and connected in a series to resistor element r0.
Unit circuits rsum1˜rsum5 are composed of transistors p1˜p5, respectively, and are of a binary configuration in which the impedances Rsum1˜Rsum5 of each of these unit circuits are in the following relation:Rsum1=Rsum2/2=Rsum3/4=Rsum4/8=Rsum5/16
The relationships between the width w of transistors p1˜p5 and resistances Rp1˜Rp5 of resistance components rp1˜rp5 and capacitances Cp1˜Cp5 of capacitance components cp1˜cp5 of transistors p1˜p5 are identical to the third example of the prior art.
FIG. 7A shows the state in which the two transistors p1 and p2 are ON and the termination resistance of the entire on-die termination circuit with respect to the terminal pin is adjusted to 50Ω. In this case, R0 is assumed to be 25Ω and Rp1 is assumed to be approximately 37.5Ω. In contrast, FIG. 8A shows a case in which, because the termination resistance is fabricated somewhat low, the two transistors p1 and p3 are ON and the termination resistance is adjusted to 50Ω. In this case, R0 is assumed to be approximately 20Ω.
In the case of FIG. 7A, impedances Rsum1˜Rsum5 of unit circuits rsum1˜rsum5, for a case that takes the frequency characteristic into consideration, can be represented as follows:
            Rsum      ⁢                          ⁢      1        =                  Rp        ⁢                                  ⁢        1            //                        1          /          sCp                ⁢                                  ⁢        1        ⁢        on                        Rsum      ⁢                          ⁢      2        =                            R          ⁢                                          ⁢          2                +                  (                                    Rp              ⁢                                                          ⁢              2                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  2                  ⁢                  on                                )                                              )                    ⁢                          ⁢                          =                        2          ×          R          ⁢                                          ⁢          1                +                  (                                    2              ×              Rp              ⁢                                                          ⁢              1                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  1                  ⁢                                      on                    /                    2                                                  )                                              )                                Rsum      ⁢                          ⁢      3        =                            R          ⁢                                          ⁢          3                +                  1          /                      (                          sCp              ⁢                                                          ⁢              3              ⁢              off                        )                              =                        4          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                4                                      )                                          Rsum      ⁢                          ⁢      4        =                            R          ⁢                                          ⁢          4                +                  1          /                      (                          sCp              ⁢                                                          ⁢              4              ⁢              off                        )                              =                        8          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                8                                      )                                          Rsum      ⁢                          ⁢      5        =                            R          ⁢                                          ⁢          5                +                  1          /                      (                          sCp              ⁢                                                          ⁢              5              ⁢              Off                        )                              =                        16          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                16                                      )                              
Similarly, in the case of FIG. 8A, impedances Rsum1˜Rsum5 of unit circuits rsum1˜rsum5, for a case that takes the frequency characteristic into consideration, can be represented as follows:
            Rsum      ⁢                          ⁢      1        =                  Rp        ⁢                                  ⁢        1            //                        1          /          sCp                ⁢                                  ⁢        1        ⁢        on                        Rsum      ⁢                          ⁢      2        =                            R          ⁢                                          ⁢          2                +                  1          /                      (                          sCp              ⁢                                                          ⁢              2              ⁢              off                        )                              =                        2          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢              off              ⁢                              /                            ⁢              2                        )                                          Rsum      ⁢                          ⁢      3        =                            R          ⁢                                          ⁢          3                +                  (                                    Rp              ⁢                                                          ⁢              3                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  3                  ⁢                  on                                )                                              )                    ⁢                          ⁢                          =                        4          ×          R          ⁢                                          ⁢          1                +                  (                                    4              ×              Rp              ⁢                                                          ⁢              1                        //                          1              /                              (                                  sCp                  ⁢                                                                          ⁢                  1                  ⁢                                      on                    /                    4                                                  )                                              )                                Rsum      ⁢                          ⁢      4        =                            R          ⁢                                          ⁢          4                +                  1          /                      (                          sCp              ⁢                                                          ⁢              4              ⁢              off                        )                              =                        8          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                8                                      )                                          Rsum      ⁢                          ⁢      5        =                            R          ⁢                                          ⁢          5                +                  1          /                      (                          sCp              ⁢                                                          ⁢              5              ⁢              off                        )                              =                        16          ×          R          ⁢                                          ⁢          1                +                  1          /                      (                          sCp              ⁢                                                          ⁢              1              ⁢                              off                /                16                                      )                              
In addition, the impedance RTerm of the entire on-die termination circuit with respect to the terminal pin can be represented as follows:RTerm=R0+(Rsum1//Rsum2//Rsum3//Rsum4//Rsum5)
FIG. 9 shows the results of plotting RTerm against frequency in each of the cases of FIG. 7A and FIG. 8A.
As shown in FIG. 9, R_lower, which is the minimum value of RTerm, is the impedance stabilization point in the high-frequency region, as in the third example of the prior art. This R_lower converges on resistance R0 of main resistor element r0 in the case of both FIG. 7A and FIG. 8A.
In other words, impedance RTerm of the high-frequency region is 25Ω in the case of FIG. 7A and 20Ω in the case of FIG. 8A.
The frequency dependence of the termination resistance is therefore great in the fourth example of the prior art, and impedance RTerm at which stability is attained in the high-frequency region is considerably lower than the target of 50Ω in either of the cases of FIG. 7A and FIG. 8A. The divergence between the termination resistance in the case of FIG. 8A (R0=20Ω) and the termination resistance in the case of FIG. 7A (R0=25Ω) is as great as 25%, but even if the divergence is reduced to the order of 10% (R0=22Ω), impedance RTerm at which stability is attained is still approximately 22Ω and is thus considerably lower than the target of 50Ω.
Because the transistors that are ON during adjustment of the termination resistance differ in the case of FIG. 7A and the case of FIG. 8A and the parasitic element configuration of these portions consequently differ, the frequency characteristics change and impedance RTerm at which stability is attained varies greatly. In the fourth example of the prior art, however, resistances Rp1˜Rp5 of transistors p1˜p5 must be set higher than in the third example of the prior art (Rp1=37.5Ω in the case of FIG. 7A), whereby the size (width) of transistors p1˜p5 is smaller, and change in the frequency characteristics is also smaller.
As previously explained, the termination resistance is highly dependent on frequency when adjusting the termination resistance in an on-die termination circuit of the prior art, and the prior art therefore suffers from the problem that the termination resistance is lower than the target value in the high-frequency region.
A difference in the transistors that are ON when adjusting the termination resistance raises the problem that the parasitic element configuration of these parts also differs, whereby the frequency characteristic changes and the termination resistance at which stability is attained in the high-frequency region varies greatly.